Techniques for sequential circuit automatic test generation
Niermann, Thomas Michael
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https://hdl.handle.net/2142/22192
Description
Title
Techniques for sequential circuit automatic test generation
Author(s)
Niermann, Thomas Michael
Issue Date
1991
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical and Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Test pattern generation has progressed to a stage at which automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. While scan-based approaches can convert the sequential circuit into a combinational circuit for testing purposes, the cost of a complete scan design methodology can be prohibitive in both area overhead and performance degradation. Therefore, an efficient sequential circuit test generation system which generates tests for all detectable faults and identifies all untestable faults in the original design is necessary. The information on untestable faults could be used to add minimal design for test hardware to make these faults testable.
This thesis presents several new techniques to improve the performance of sequential circuit test generators. Among the concepts presented are unnecessary state elimination, and the use of fault simulation knowledge to increase test coverage during a second phase of test generation, a targeted D element technique for D propagation, and the use of the good circuit state knowledge. The concepts presented in the thesis were implemented and tested on the ISCAS sequential benchmark circuits.
This thesis presents an improved fault simulation algorithm based on a combination of the parallel, concurrent and differential fault simulation algorithms. This fault simulator is shown to require much less memory while being 6 to 67 times faster than a traditional concurrent fault simulator.
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