Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability
Leblebici, Yusuf
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Permalink
https://hdl.handle.net/2142/21963
Description
Title
Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability
Author(s)
Leblebici, Yusuf
Issue Date
1991
Doctoral Committee Chair(s)
Kang, Sung Mo
Department of Study
Electrical and Computer Engineering
Discipline
Electrical and Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
In this thesis, an integrated simulation approach is presented for estimating the hot-carrier induced degradation of MOSFET device characteristics and circuit performance. The proposed simulation tool provides information on (i) the evolution of device and circuit performance degradation during long-term dynamic operation, (ii) the amount of hot-carrier induced damage in each transistor after a specified operation period, and (iii) the performance characteristics of the damaged circuit. This information can be used both for understanding the circuit-level dynamics of the degradation mechanisms and as a design aid, for improving the long-term circuit reliability through design modifications.
Simple simulation models for the hot-carrier related degradation mechanisms in nMOS transistors are proposed. The physical degradation models include all of the significant mechanisms, i.e. electron- and hole trapping, interface trap generation by electron injection and interface trap generation by hole injection. The separate treatment of the charge trapping and interface trap generation mechanisms is a novel approach in degradation modeling which is increasingly supported by recent experimental evidence. A dynamic interface trap generation model is derived, and the fundamental differences between static and dynamic stress characteristics are discussed in detail.
An accurate one-dimensional device model is also presented for the simulation of nMOS transistors with hot-carrier induced oxide damage. The model accounts for the localization of the oxide-interface charge near the drain, and it uses a realistic charge density distribution profile to represent the exact behavior of the transistor in the linear region as well as in the saturation region. The amount and the location of the hot-carrier induced oxide damage are introduced by changing only a few parameters, which simplifies the implementation of the model in a reliability simulation environment. The proposed model has been implemented in the iSMILE circuit simulator, and the capabilities of the model have been explored by various circuit simulation examples.
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