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https://hdl.handle.net/2142/21902
Description
Title
The testability of regular logic structures
Author(s)
Chatterjee, Abhijit
Issue Date
1990
Doctoral Committee Chair(s)
Abraham, Jacob A.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
The use of regular logic structures has become very important in the recent past due to the complexity of the circuits that are being fabricated and the need to design, test and debug them. The testability of different classes of regular logic structures that are widely used in many practical applications is investigated in this thesis. The first class of circuits that is considered is called generalized counters. These are complex tree-structured circuits and can be represented by recursive mathematical equations. They do not possess rigid topological regularity. The testability of these circuits is investigated under the assumption of single as well as multiple faulty cells. A circuit design methodology is proposed that results in easily testable circuits when single faulty cells are assumed to occur. The second class of circuits examined is that of iterative logic arrays which are widely used in computer arithmetic hardware. The issues of design-for-testability, built-in self-test as well as automatic test generation for these circuits are discussed. The techniques developed are far more powerful and general than those conceived by previous researchers. A test generation program for iterative logic arrays that is the first of its kind to be written is discussed. The test generation problem for one-dimensional sequential arrays of cells is also analyzed. Such arrays, called bit-serial arrays, are widely used in many digital signal processing applications.
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