Time-based strategies for semiconductor manufacture and test
Levitt, Marc Elliot
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https://hdl.handle.net/2142/21879
Description
Title
Time-based strategies for semiconductor manufacture and test
Author(s)
Levitt, Marc Elliot
Issue Date
1990
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Operations Research
Language
eng
Abstract
The world is a more competitive place than before, and time is a key component in any winning competitive strategy. This thesis provides methods by which companies can become more efficient time-based competitors in the semiconductor and computer businesses. Methods are presented in two very important areas, design and manufacture.
In the design area, the issues of test and design-for-test are examined since they are important and growing parts of the total design cycle. A productivity study is presented and, from the insight gained, models are developed to accurately predict important issues in test and design-for-test. The productivity models are then combined with economic models to achieve a complete life cycle picture of the integrated circuit that not only includes die economics but also time-to-market effects and quality issues. Examples are presented to demonstrate the use of the models.
In the manufacturing end of the semiconductor business, a method is developed that allows just-in-time techniques to be applied to fabrication areas. The technique consists of unraveling the job shop by concentrating on the bottleneck and/or critical workstations and then calculating the number of Kanban cards needed to control inventory and production. An extensive simulation-based evaluation of the method is presented, comparing it to many other techniques for three types of fabrication areas. These are: single bottleneck with no hot-lots, multiple bottlenecks with no hot-lots, and single bottleneck with hot-lots. In all cases the just-in-time method developed performs best overall.
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