A high-level approach to test generation for VLSI circuits
Narain, Prakash
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https://hdl.handle.net/2142/21690
Description
Title
A high-level approach to test generation for VLSI circuits
Author(s)
Narain, Prakash
Issue Date
1992
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
The traditional approaches to test generation made use of the gate level representation of the circuit. This test generation problem is known to be NP-Complete for combinational circuits. A high level test generation approach has been designed on the basis of the branch and bound search procedure. This approach contains a data path test generator and a control circuit test generator.
The data path is modeled using a data flow graph. The gate level test generation concepts of propagation, justification and implication have been extended to high level. A dependency directed backtracking scheme has been designed for the algorithm.
The control circuit for test generation is modeled as a gate level interconnection of primitives. The data path is modeled as a high level interconnection. A sequential circuit test generation algorithm has been designed based upon forward time processing. A novel concept of initialization inference has been introduced.
Both of the approaches have been demonstrated to be very effective.
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