Probabilistic simulation for reliability analysis of VLSI circuits
Najm, Farid Nasri
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https://hdl.handle.net/2142/21610
Description
Title
Probabilistic simulation for reliability analysis of VLSI circuits
Author(s)
Najm, Farid Nasri
Issue Date
1989
Doctoral Committee Chair(s)
Hajj, Ibrahim N.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
This thesis presents a new technique for simulating integrated circuits, called probabilistic simulation. Using this technique, statistical descriptions of the voltage waveforms at the circuit primary inputs are used to derive corresponding statistical descriptions of the internal voltages and currents. To illustrate its utility, we use this approach to analyze integrated circuit reliability. Specifically, we focus on the problem of predicting the susceptibility of a given design to electromigration failures.
We show that the median time-to-failure (MTF), due to electromigration, can be related to a stochastic model of the power supply and ground currents. Most of the thesis is then devoted to explaining the probabilistic simulation technique, adapted to CMOS VLSI digital circuits, and how it can be used to derive the required statistical descriptions of the current. This approach has been implemented in the program CREST, and has shown excellent accuracy and dramatic speedups compared to traditional approaches. We describe the probabilistic simulation technique and its implementation, and present the results of CREST runs on a variety of circuits.
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