Optimal state assignment of sequential circuits using a genetic local search with flexible cost functions
Olson, Eric Peter
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Permalink
https://hdl.handle.net/2142/21498
Description
Title
Optimal state assignment of sequential circuits using a genetic local search with flexible cost functions
Author(s)
Olson, Eric Peter
Issue Date
1995
Doctoral Committee Chair(s)
Kang, Sung Mo
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
In this dissertation, we solve the finite state machine (FSM) state assignment problem using an implementation of a genetic local search algorithm (GLS) that selectively targets design goals with the use of flexible cost functions. Our GLS quickly converges toward a globally optimal state encoding, producing high quality solutions. We explore the properties of encoding-based (calculated from the encoding values) and synthesis-based (calculated from synthesis results) cost functions. With these functions, the GLS consistently finds the best known encoding solutions with FSMs of less than sixty states and very good assignments for larger benchmarks.
The encoding-based functions reduce the number of literals and/or reduce the transition density of the state bits. The designs produced from these encodings were 11% smaller and consumed 10% less power than the designs from state-of-the-art state assignment tools. The inaccuracy inherent in any encoding-based cost function limits its application. We have overcome such inaccuracy by using cost functions based on actual synthesis. Area, power, and delay estimates are obtained by optimizing and mapping the encoding. The GLS allows synthesis-based cost functions to steer its selection so that the desired qualities of a solution can be preserved. We found empirically that our recombination procedure allowed the GLS to converge upon solutions with desired area, power, or delay characteristics with synthesis-based cost functions. Results for the MCNC benchmarks showed that these encodings produced circuits that were 21% smaller in area and 30% lower in power than those from state-of-the-art encoding tools. Furthermore, the synthesis-based cost functions produce encodings that lead to circuits with 20% less delays than for the state-of-the-art encoding tools.
This dissertation provides an understanding of the relationship between state assignment and synthesis in terms of area, power, and delay. We describe a probabilistic power estimation tool for sequential circuits. We derive an accurate power estimate based on a zero-delay gate model of the design. This tool preserves all spatial and temporal correlations specified in the FSM description and eliminates the effects of reconvergent fanout. This tool is shown to be sufficiently fast enough to be used for cost calculation and accurate for design quality evaluation.
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