Design and synthesis for testability using architectural descriptions
Chickermane, Vivekanand
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Permalink
https://hdl.handle.net/2142/21301
Description
Title
Design and synthesis for testability using architectural descriptions
Author(s)
Chickermane, Vivekanand
Issue Date
1993
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
The increasing use of high-level description languages, such as VHDL, to design large VLSI circuits has opened up some interesting research possibilities. It is now feasible to locate hard-to-test areas of a large circuit early in the design phase prior to logic synthesis. The main goal of this research is to judiciously and effectively use architectural descriptions to design and synthesize easily testable circuits. An architectural description consists of a hierarchical structural specification of the datapath and a behavioral description of the control unit. A software tool to automatically extract the pertinent high-level information from VHDL and synthesize testable circuits is described. Since testability is inserted at a high level, some of the limitations of gate-level methods are overcome.
The second objective of this research is to perform a comparative study of a gate-level and a high-level test generator by benchmarking them on a common suite of circuits. This study has shown that a high-level design-for-testability tool can make a more efficient and effective selection of partial scan flip-flops. It can accurately predict the hard-to-test areas of a circuit. Significant improvements in fault coverage and test generation efficiency, and speedups in test generation time can be achieved.
When a logic module is embedded in a large circuit, the high-level functional constraints usually cause don't cares at the interface of the embedded module. If the logic of the module is not synthesized using these don't cares, then redundancy may exist, making the circuit very hard to test. The third objective of this research is to identify the functional constraints and then extract the don't cares. Compiler optimization techniques are used to compact the derived information and to extract don't cares for each embedded module. The logic of the module can then be optimized and redundancies can be removed.
Finally, some at-speed design for testability techniques which permit a circuit to be tested at its operational speed are investigated. Some of the techniques used to select partial scan flip-flops at the high level can be easily amended to permit nonscan testability insertion. An important consequence is that the original high-level circuit description can be altered to reflect the changes made later in the design phase. This will keep the final circuit description consistent with the high-level description which is important for the purposes of simulation and verification.
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