Modeling and simulation of electrical overstress failures in input/output protection devices of integrated circuits
Diaz, Carlos Hernando
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https://hdl.handle.net/2142/21266
Description
Title
Modeling and simulation of electrical overstress failures in input/output protection devices of integrated circuits
Author(s)
Diaz, Carlos Hernando
Issue Date
1993
Doctoral Committee Chair(s)
Kang, Sung Mo
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
It is proposed in this thesis that a measure to determine the electrical overstress (EOS) hardness of integrated circuits with respect to EOS/electrostatic discharge (ESD) can be measured in terms of the power vs. time-to-failure relationship (power profile) and the current vs. time-to-failure relationship (current profile).
A new nonlinear mixed 2D-1D thermal simulator, iTSIM, was developed in order to understand and quantify the sensitivity of the power profiles with respect to major thermal parameters of the integrated circuit (IC).
Protection devices with different layout parameters were fabricated and experimentally characterized for EOS. Experimental data indicate that these devices fail with a poly gate filament in the drain edge when subjected to ESD or short-duration EOS events, while extensive device damage is observed for long-duration EOS events revealing onset of thermal runaway. Two-dimensional (2D) device-level electrothermal simulations are used to develop qualitative analysis of both the physical mechanisms leading to device failure and the dependencies of the failure thresholds (power and current profiles) on the layout parameters. Results from this study coupled with heat removal considerations led to a design guideline for source contact placement that is expected to improve the failure thresholds for I/O protection devices of CMOS ICs with grounded substrate.
Thermal instability of an electrically stressed circuit or device is shown to be the result of either thermally induced negative differential resistance (NDR) in resistive regions, or junction second breakdown. Under typical ESD/EOS stress events (transient in nature), the temperature at which thermal instability takes place depends on the level of the stress current. In semiconductor junctions reverse-biased by an EOS event, second breakdown is shown to happen at the time when thermal carrier generation becomes high enough to offset the effects of the mobility degradation and the reduction of the impact ionization rates. Under these circumstances, the time for the onset of second breakdown is shown to depend on the device's geometry and the level of power dissipation.
Circuit level electrothermal models are introduced for resistors, diodes, and bipolar and MOS transistors; they are capable of describing device behaviour up into thermal runaway or second breakdown. (Abstract shortened by UMI.)
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