Compiler-directed cache coherence strategies for large-scale shared-memory multiprocessor systems
Cheong, Hoichi
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https://hdl.handle.net/2142/21265
Description
Title
Compiler-directed cache coherence strategies for large-scale shared-memory multiprocessor systems
Author(s)
Cheong, Hoichi
Issue Date
1990
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
The cache coherence maintenance problem has been the major obstacle in using private cache memory to reduce memory access latency in large-scale multiprocessor systems. Two compiler-directed solutions, the fast selective invalidation scheme and the version control scheme, are proposed in this work. Contrary to the existing hardware-based approach, the proposed schemes expose caches to software-directed management techniques which have the advantage of requiring no global communication and maintaining expandability of the multiprocessor systems. The fast selective scheme employs compile-time flow analysis techniques to detect cache data that contain obsolete values, and uses simple hardware to prevent using such data. The version control scheme defines the concept of version of a program variable to maintain up-to-date copies in the cache and solves the difficult problem of preserving temporal locality in parallel execution. Unlike existing software-directed schemes, both schemes achieve selective invalidation with very low time penalty. The version control scheme is also extended to hierarchical cache systems for which no satisfactory solutions exist. Detailed discussion on the development of these schemes and their proofs are presented. Finally, experimental data by simulation are shown to support the advantage of the schemes.
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