Simulation-based techniques for sequential circuit testing
Rudnick, Elizabeth Marie
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Permalink
https://hdl.handle.net/2142/21077
Description
Title
Simulation-based techniques for sequential circuit testing
Author(s)
Rudnick, Elizabeth Marie
Issue Date
1994
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Fault simulators are used extensively in the design of electronic circuits for both testing and fault diagnosis. Complex component types can be easily handled in a fault simulator, since processing occurs in the forward direction only, and various fault models can be accommodated. This research is targeted toward exploiting fault simulation for test generation, design for testability, and fault diagnosis. An existing sequential circuit fault simulator is used, and extensions to the fault simulator for these application areas are described.
A nonscan observability enhancement approach is presented, which uses the fault simulator to select a minimal set of probe points for detection of faults previously found to be untestable due to observability problems. This method can be combined with nonscan controllability enhancement techniques to provide high fault coverages without affecting the ability to do at-speed testing. The fault simulator is also extended to provide information about the diagnostic capability of a test set and to diagnose failing devices, given the actual output responses. Next, simulation-based test generation is explored as an alternative to deterministic approaches. A genetic algorithm (GA) framework is interfaced to the fault simulator to generate test sets with high fault coverages. The GA generates populations of candidate test vectors or test sequences, and the fault simulator is used to evaluate the fitness of each test. Various GA parameters are studied, and methods to achieve low execution times are discussed. Generation of test sets for full scan and partial scan circuits which limit the scan operations are also described. Test application time for scan circuits can be long, but reductions can be made if flip-flop values are not scanned in and out before and after every test vector is applied. Finally, the GA framework is combined with a deterministic test generator for sequential circuits. The hybrid test generator uses deterministic algorithms for fault excitation and propagation and a GA for state justification. Existing deterministic procedures for state justification are used only if the genetic approach is unsuccessful. This hybrid approach allows for higher fault coverages while providing for identification of untestable faults.
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