Automatic test generation for bit-serial VLSI digital signal processors
Roy, Rabindra Kumar
This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.
Permalink
https://hdl.handle.net/2142/20975
Description
Title
Automatic test generation for bit-serial VLSI digital signal processors
Author(s)
Roy, Rabindra Kumar
Issue Date
1992
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Linear digital signal processors, commonly implemented using silicon compilers in bit-serial architecture, are very difficult to test for manufacturing defects due to deep sequentiality, low controllability and observability, and high latency. A novel hierarchical testing approach has been proposed, integrating three automatic test generators. FEAST (Functional Extractor and Sequential Test generator) operates at the high level, where the circuit is described as an interconnection of arithmetic modules. SEAT (Sequential Array Test generator) and CREST (Constrained Sequential Test generator) operate at the low level description of the individual modules.
FEAST extracts various matrices corresponding to the state space description of the circuit, and the functional constraints that must be satisfied the inputs of the module under test (MUT). The constraints and the description of the MUT are passed to CREST, which generates tests in the binary domain. FEAST translates these tests into the numerical domain to find the numbers to be applied at the primary inputs to achieve the tests at the inputs of the MUT. Since the binary representation of these numbers are inexact due to truncation and roundoff, a novel search-based correction scheme is employed to get the exact solution in binary.
SEAT operates on array structures and attempts to generate repetitive tests to apply comprehensive checking experiments to finite state machines within individual cells of the array. SEAT has been very successful on one-dimensional sequential arrays and outperformed an efficient automatic gate-level test generator.
The performance of FEAST and CREST was compared with two other approaches, namely automatic test generation at gate level and random test pattern generation for several large circuits. The new techniques recorded the best combination of all of the performance metrics, namely, fault coverage, test efficiency, test length, and computational time.
Use this login method if you
don't
have an
@illinois.edu
email address.
(Oops, I do have one)
IDEALS migrated to a new platform on June 23, 2022. If you created
your account prior to this date, you will have to reset your password
using the forgot-password link below.
