Scheduling and allocation problems in high-level synthesis
Kim, Taewhan
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Permalink
https://hdl.handle.net/2142/20327
Description
Title
Scheduling and allocation problems in high-level synthesis
Author(s)
Kim, Taewhan
Issue Date
1993
Doctoral Committee Chair(s)
Liu, C.L.
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Applied Mechanics
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.
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