Design automation for high performance complementary metal oxide-semiconductor VLSI circuits
Chen, Hau-Yung
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Permalink
https://hdl.handle.net/2142/20223
Description
Title
Design automation for high performance complementary metal oxide-semiconductor VLSI circuits
Author(s)
Chen, Hau-Yung
Issue Date
1989
Doctoral Committee Chair(s)
Kang, Sung Mo
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
This thesis addresses the circuit and layout issues of the Complementary Metal-Oxide-Semiconductor (CMOS) Very Large Scale Integrated (VLSI) circuit design. Dynamic CMOS circuits are implemented judiciously to increase the packing density and lower the power consumption. A design automation system, iCOACH, which dynamically generates cells as needed for each job according to their circumstantial situations such as fan-in, fan-out, and input signals is developed. A nonlinear objective function based on the technology power concept is formulated to determine the best circuit speed/area ratio. The reliability issues such as the charge sharing and the noise margin problems are embedded in the design constraints along with transistor size and timing specification constraints.
Since optimization itself is a computationally expensive process which requires repeated calculations of delay and area at each iteration step, it would be prohibitive for large circuits is there were other iterations involved besides the optimization process itself. To avoid expensive circuit level simulation, an analytical delay model is developed to quickly estimate the delay time. Unlike the traditional RC delay models, this analytical delay model is derived from device parameters and I-V characteristics and achieves an accuracy of less than 10% error as compared to SPICE simulations. Large size circuits are handled by first allocating the timing specification to individual cells based on the sensitivity of the delay time to the silicon area.
A folding layout style for dynamic functional cells is presented. This layout style provides an efficient usage of the silicon resources for all unbalanced circuit structures such as dynamic CMOS and nMOS and compatible with that of the static CMOS circuit in the polycell layout environment. As a result, dynamic and static circuits can be mixed efficiently in a circuit and the existing placement and routing tools can still be applied.
A 4-bit ALU and a 32-bit adder circuit examples are shown to demonstrate the capability of the system.
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