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https://hdl.handle.net/2142/19825
Description
Title
Logic optimization of MOS networks
Author(s)
Limqueco, Johnson Chan
Issue Date
1992
Doctoral Committee Chair(s)
Muroga, Saburo
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
The logic networks that can be put on a single chip continues to grow in size and complexity. There is thus an increasing need for designers to rely on the assistance of computer-aided design tools to provide a fast design turnaround and reduce design errors. Logic design (or logic synthesis) is one major step in the ASIC VLSI design cycle in which automation is playing an increasingly important role in recent years. In this thesis, we describe an algorithm, SYLON-REDUCE, that can be used in automated logic synthesis tools for the logic optimization of MOS networks.
Most existing logic synthesis algorithms divide logic synthesis into a technology-independent logic synthesis and optimization phase and a technology-mapping phase. This, however, may yield suboptimal final networks. In contrast to this two-phase design approach, SYLON-REDUCE uses a technology-specific approach for the logic optimization of multi-level combinational MOS networks. Given an initial MOS network, SYLON-REDUCE resynthesizes each cell in the network and produces an area- or delay-optimized network which contains only cells that satisfy the same technology constraints or belongs to the same technology library as the cells in the initial network. SYLON-REDUCE uses the concept of permissible functions for more effective optimization. Extensive experimental results demonstrate the effectiveness of SYLON-REDUCE, which generally produces better results than other existing algorithms, including those that employ a two-phase design approach.
To make SYLON-REDUCE applicable to a wider range of large, complex networks, we use a windowing scheme for repeated local optimization of these large networks. This scheme also enables the algorithm to optimize the delay of these networks effectively. Experimental results prove this to be a viable approach.
Furthermore, SYLON-REDUCE is useful for further improvement of MOS technology-mapped networks. It will also be particularly useful in cell generation or full custom design environments.
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