Compiler support for multiple-instruction-issue architectures
Chang, Po-hua
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https://hdl.handle.net/2142/19554
Description
Title
Compiler support for multiple-instruction-issue architectures
Author(s)
Chang, Po-hua
Issue Date
1991
Doctoral Committee Chair(s)
Hwu, Wen-Mei W.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
This dissertation demonstrates that substantial speedup over that for conventional single-instruction-issue architectures can be achieved by multiple-instruction-issue architectures with the support of an optimizing compiler. We have constructed a full-scale C compiler that can learn the dynamic behavior of user programs by profiling, apply the profile information to guide various code improving techniques, and map the program parallelism onto the parallel architecture. Our base code optimization technology is comparable to today's best commercial C compilers. In addition, we have developed aggressive code generation techniques that are tailored to multiple-instruction-issue architectures. Using our compiler, we have characterized the performance of a large class of multiple-instruction-issue architectures with many important application programs and realistic input data.
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