Performance-driven chip floorplanning and global routing
Prasitjutrakul, Somchai
This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.
Permalink
https://hdl.handle.net/2142/19413
Description
Title
Performance-driven chip floorplanning and global routing
Author(s)
Prasitjutrakul, Somchai
Issue Date
1991
Doctoral Committee Chair(s)
Kubitz, William J.
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
In this thesis algorithms for solving performance-driven chip floorplanning and global routing problems in physical VLSI design are presented. Interconnection delays are estimated and directly incorporated into the problem formulations. A timing analysis provides timing information consisting of a set of potentially critical paths and the delay slacks of the signal nets. This information is used to maintain path delays within bounds and to minimize the delay of the most critical path, while satisfying other geometrical design constraints and objectives. This performance-driven chip floorplanning methodology starts by assigning off-chip I/O's to I/O pads on the periphery of the chip. Next initial module placement, which minimizes the most critical path delay as well as the total net length, while satisfying the timing and geometrical constraints, is determined. Then the positions, shapes and orientations of the modules are adjusted, based on the information obtained from the module adjacency graphs, in order to minimize the chip area while simultaneously avoiding timing problems and preserving the initial relative module positions. The performance-driven global routing scheme uses the remaining net delay slack as the main parameter to guide the routing. It is shown that when interconnection resistance is considered, minimizing the total net length is not always equivalent to minimizing the net delay for multiterminal nets.
Use this login method if you
don't
have an
@illinois.edu
email address.
(Oops, I do have one)
IDEALS migrated to a new platform on June 23, 2022. If you created
your account prior to this date, you will have to reset your password
using the forgot-password link below.
