University of Illinois Urbana-Champaign

Hardware and software for functional and fine-grain parallelism

Beckmann, Carl Josef

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https://hdl.handle.net/2142/19412

Description

Title
Hardware and software for functional and fine-grain parallelism
Author(s)
Beckmann, Carl Josef
Issue Date
1993
Doctoral Committee Chair(s)
Polychronopoulos, Constantine D.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
  • Engineering, Electronics and Electrical
  • Computer Science
Language
eng
Abstract
  • This thesis examines nonloop parallelism at both fine and coarse levels of granularity in numerical FORTRAN programs. Measurements of the extent of this functional parallelism in a number of FORTRAN codes are presented, as well as compiler and run-time algorithms designed to exploit it. Hardware and software embodiments of the dynamic scheduling algorithms are developed, along with the compiler optimizations necessary to make these practical.
  • The impact of fine grain functional parallelism on instruction-level architecture is explored, and it is shown that dynamic instruction scheduling hardware based on the functional parallelism scheduling algorithms can yield a significant improvement over static scheduling on conventional RISC processors when the latency of memory accesses is highly variable. Measurements of the characteristics of a set of FORTRAN benchmark programs indicates that such a hardware realization is feasible in practice.
Type of Resource
text
Permalink
http://hdl.handle.net/2142/19412
Copyright and License Information
Copyright 1993 Beckmann, Carl Josef

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