iSITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits
Gee, Perry
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https://hdl.handle.net/2142/19216
Description
Title
iSITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits
Author(s)
Gee, Perry
Issue Date
1989
Director of Research (if dissertation) or Advisor (if thesis)
Hajj, Ibrahim N.
Doctoral Committee Chair(s)
Hajj, Ibrahim N.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Very large scale integrated (VLSI) circuit technology allows one to manufacture chips with several million devices. Designing such large circuits cannot be accomplished without design automation tools and computer-aided design tools. This thesis addresses the problem of automatic circuit synthesis for double-metal CMOS technology. Large circuits are partitioned into cells and represented as incidence matrices. The rows and columns of these matrices are folded to minimize the area. A symbolic layout is then generated for each matrix. This symbolic layout is then used to generate the physical mask layers necessary for fabrication in the metal-metal matrix methodology.
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