Advanced techniques for fast timing simulation of MOS VLSI circuits
Dharchoudhury, Abhijit
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Permalink
https://hdl.handle.net/2142/19213
Description
Title
Advanced techniques for fast timing simulation of MOS VLSI circuits
Author(s)
Dharchoudhury, Abhijit
Issue Date
1995
Doctoral Committee Chair(s)
Kang, Sung Mo
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
The basic goals of the research presented in this thesis are to remove various shortcomings in existing fast timing simulators and to extend the scope and applicability of fast timing simulation to submicron digital circuits. Existing fast timing simulators have been shown to be extremely efficient in simulating large digital circuits compared to classical electrical-level simulators. However, these simulators have a number of accuracy-related problems: inaccurate MOS modeling, inadequate consideration of the effects of internal nodes in complex logic gates and of interconnect loading, etc. The thrust of this dissertation is in the investigation of techniques that will allow us to remove these shortcomings while preserving, as much as possible, the simulation efficiency.
To this end, a regionwise quadratic (RWQ) modeling technique that allows arbitrary MOS drain current models to be used in fast timing simulation applications has been developed. This technique considerably improves the accuracy of the models and the simulation results, while retaining the characteristics of the macromodels that enable fast and efficient solution techniques to be applied. The issue of internal nodes in complex logic gates is addressed and a technique based on waveform relaxation that enables these internal nodes to be simulated accurately has been developed. This method is applicable to circuits exhibiting complex interactions between multiple circuit nodes as well as to circuits in which internal nodes are inputs to subsequent logic stages. A novel and accurate effective capacitance calculation technique to account for the effect of interconnects on nonlinear driver gates is proposed. This technique accurately predicts the delays and shapes of driver output waveforms under interconnect loading without adding any computational overhead. A novel method for incremental fast timing simulation and transient sensitivity analysis is also described. It is shown that in applications requiring a large number of closely related transient analyses, the incremental simulation technique can provide accurate results with a substantial reduction in computational cost. Finally, an application of the fast timing simulation technique to the simulation of transient faults is discussed.
The methodologies and techniques developed in this thesis have been implemented in a fast timing simulator called ILLIADS2. The application of ILLIADS2 on a number of MOS circuits is demonstrated.
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