Fault sensitivity and wear-out analysis of VLSI systems
Choi, Gwan Seung
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Permalink
https://hdl.handle.net/2142/19060
Description
Title
Fault sensitivity and wear-out analysis of VLSI systems
Author(s)
Choi, Gwan Seung
Issue Date
1994
Doctoral Committee Chair(s)
Iyer, Ravishankar K.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Aerospace
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
This thesis describes simulation approaches to conduct fault sensitivity and wear-out failure analysis of VLSI systems. A fault-injection approach to study transient impact in VLSI systems is developed. Through simulated fault injection at the device level and subsequent fault propagation at the gate, functional and software levels, it is possible to identify critical bottlenecks in dependability. Techniques to speed up the fault simulation and to perform statistical analysis of fault impact are developed. A wear-out simulation environment is also developed to closely mimic dynamic sequences of wear-out events in a device through time, to localize weak location/aspect of target chip and to allow generation of Time-to-Failure (TTF) distribution of a VLSI chip as whole. First, an accurate simulation of a target chip and its application code is performed to acquire real workload trace data on switch activity. Then, using this switch activity information, wear-out of the each component of the chip is simulated using Monte Carlo techniques.
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