Parallel algorithms for CAD with applications to circuit extraction
Belkhale, Krishna P.
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Permalink
https://hdl.handle.net/2142/19035
Description
Title
Parallel algorithms for CAD with applications to circuit extraction
Author(s)
Belkhale, Krishna P.
Issue Date
1991
Doctoral Committee Chair(s)
Banerjee, Prithviraj
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
As the sizes of VLSI circuits increases in the future, the computational requirements for performing various computer-aided design (CAD) tasks will increase tremendously. In this thesis, we look at the application of parallel processing to computer aided design problems, with special emphasis to the problem of VLSI circuit extraction. We first describe parallel algorithms for VLSI circuit extraction on hypercube and shared memory multiprocessors. We give the performance results of the algorithms on an Intel iPSC2 hypercube and an Encore Multimax shared memory multiprocessor, for different partitioning strategies.
There were two sub problems in the above research that are of general importance. The first problem is called the geometric connected component labeling problem, that arises in the combining phase of parallel extraction. We describe some practical algorithms for this problem. The second problem involves maintaining recursively partitioned data structures of points on distributed memory multiprocessors, under the operations of addition and deletion of points. This problem arises when partitioning strategies are considered, that divide a circuit so that the resulting sub regions have approximately the same number of rectangles. We describe two algorithms for this general problem, and analyze their complexity.
The next step is to take a general look at the use of hierarchical methods in computer-aided design. We describe how the benefits of hierarchical analysis and parallelism can be combined. Towards this goal, we formulate the parallelizable dependent task scheduling (PDTS) problem, which is NP-hard. We describe a heuristic for the problem, and analyze its performance with respect to the optimal. We also consider a special case of the PDTS problem, wherein the tasks are independent. We present an algorithm for this problem and analyze its performance to get a better bound with respect to the optimal, as compared to the general case of the problem. This theory is then applied for a case study in parallel hierarchical circuit extraction. We present some implementation results on an Encore Multimax multiprocessor.
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