Performance-driven placement and routing algorithms
Gao, Tong
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Permalink
https://hdl.handle.net/2142/18955
Description
Title
Performance-driven placement and routing algorithms
Author(s)
Gao, Tong
Issue Date
1994
Doctoral Committee Chair(s)
Liu, C.L.
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Language
eng
Abstract
As technology advances, the effect of intra-module delays become less significant, while the effect of inter-module interconnection delays become more prominent. Also, as power dissipation becomes an important issue in VLSI design, it is desirable for the signals to arrive at the inputs of the modules at the same time in order to reduce the number of unwanted transient switches. To minimize the signal arrival times of the primary output pins and the signal skews at the inputs of the modules, we developed a net-based performance driven placement algorithm and a path-based performance driven placement algorithm. As chip architectures become more specific (e.g., FPGA), it is important to consider the physical design information during logic design steps. Therefore, we developed a placement driven technology mapping algorithm for FPGA circuits. Finally, as technology advances, interconnection wires are placed in closer proximity and circuits operate at higher frequencies. Consequently, reduction in crosstalks between interconnection wires becomes an important consideration in VLSI design. To satisfy the crosstalk constraints and to minimize the total crosstalk among all the nets in a design, we developed a track permutation algorithm for gridded channel routing problems. We also developed a wire segment assignment algorithm for both channel routing problems and switchbox routing problems. The experimental results indicate that our algorithms are very promising.
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