Distributed scalable model for CMOS FET power amplifier
Graham, Sean R.
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https://hdl.handle.net/2142/18454
Description
Title
Distributed scalable model for CMOS FET power amplifier
Author(s)
Graham, Sean R.
Issue Date
2011-01-14T22:51:23Z
Director of Research (if dissertation) or Advisor (if thesis)
Feng, Milton
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Radio Frequency (RF)+
Complementary metal–oxide–semiconductor (CMOS)
Power Amplifier
Abstract
Integrated circuits are very popular for understandable reasons. A circuit implemented within an IC is more cost effective and reliable. A vast majority of ICs are created using silicon because it is cheap and the technology is mature. Unfortunately, communications power amplifiers have been scarce, due to the electrical advantages provided by III-V semiconductors.
In order to reach similar power levels, power amplifiers implemented on silicon require larger transistors. It is common practice to create such transistors using multiple smaller transistors connected in parallel. As the frequency of operation increases, the connections between the smaller transistors affect the overall system’s behavior. Current industry standard models do not accurately compensate for these connections. This work discusses the development and results for a high-multiplicity MOS FET power amplifier model using layout transmission line considerations.
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