Redefining the hardware-software boundary in networked systems

Mochizuki, Brent A.

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https://hdl.handle.net/2142/16891 Copy

Description

Title

Redefining the hardware-software boundary in networked systems

Author(s)

Mochizuki, Brent A.

Issue Date

2010-08-20T18:00:58Z

Director of Research (if dissertation) or Advisor (if thesis)

Caesar, Matthew C.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• Internet routing
• Field-Programmable Gate Array (FPGA)
• network simulation
• network hardware
• hardware-software boundary

Abstract

While the traditional division between hardware and software development provides a useful layer of abstraction that allows developers to create complex software applications with limited knowledge of the underlying hardware, it has led to an inflexible boundary between the division of labor in hardware and software. This abstraction has been necessary to allow developers to create innovative and complex software applications efficiently, while the underlying hardware evolved separately. Recently, however, hardware design has become much simpler with the advent of high-performance programmable and reconfigurable logic. With these devices, developers now have the choice to develop custom hardware efficiently and cost-effectively. This thesis argues that developers now need to look at the boundary between hardware and software when developing performance-critical applications in networked systems. This thesis shows that, for a variety of applications, using custom hardware can be a better choice than a pure software design running on commodity hardware. To demonstrate this argument, a hardware-amenable Internet routing protocol is developed that outperforms the Border Gateway Protocol (BGP), due to its increased performance in a pure hardware implementation. To demonstrate the generality of this technique, a hardware-based network simulator is developed that can outperform ns-2 for a specific class of simulations. These implementations show that, with only a moderate amount of design complexity, hardware-aware and hardware-amenable designs can significantly improve performance.

Graduation Semester

2010-08

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http://hdl.handle.net/2142/16891

Copyright and License Information

Copyright 2010 Brent A. Mochizuki

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