Hardware acceleration for sparse Fourier image reconstruction
Dinh, Quang S.
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https://hdl.handle.net/2142/16848
Description
Title
Hardware acceleration for sparse Fourier image reconstruction
Author(s)
Dinh, Quang S.
Issue Date
2010-08-20T17:59:44Z
Director of Research (if dissertation) or Advisor (if thesis)
Bresler, Yoram
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Hardware Acceleration
Sparse Image Reconstruction
Field-Programmable Gate Array (FPGA)
Reconfigurable Computing
Abstract
Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with field-programmable gate arrays (FPGAs). The FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so that different computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. The design is estimated to provide even more speedup on a next-generation RC platform.
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