Design and implementation of a floating point unit for rigel, a massively parallel accelerator
Truty, Wojciech J.
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https://hdl.handle.net/2142/16472
Description
Title
Design and implementation of a floating point unit for rigel, a massively parallel accelerator
Author(s)
Truty, Wojciech J.
Issue Date
2010-06-22T19:37:13Z
Director of Research (if dissertation) or Advisor (if thesis)
Patel, Sanjay J.
Department of Study
Electrical & Computer Engineering
Discipline
Electrical & Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Floating point
Rigel
parallel
many core
multicore
processor
Accelerator
Floating point unit (FPU)
floating point unit
IEEE Standard for Floating-Point Arithmetic (IEEE 754)
Massively parallel
Abstract
Scientific applications rely heavily on floating point data types. Floating point operations
are complex and require complicated hardware that is both area and power intensive. The
emergence of massively parallel architectures like Rigel creates new challenges and poses new
questions with respect to
floating point support. The massively parallel aspect of Rigel places great emphasis on area efficient, low power designs. At the same time, Rigel is a general
purpose accelerator and must provide high performance for a wide class of applications. This
thesis presents an analysis of various floating point unit (FPU) components with respect to
Rigel, and attempts to present a candidate design of an FPU that balances performance,
area, and power and is suitable for massively parallel architectures like Rigel.
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