Bus scheduling implementation on the cell processor
Chivukula, Deepti K.
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https://hdl.handle.net/2142/16224
Description
Title
Bus scheduling implementation on the cell processor
Author(s)
Chivukula, Deepti K.
Issue Date
2010-05-19T18:41:07Z
Director of Research (if dissertation) or Advisor (if thesis)
Caccamo, Marco
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Bus Scheduling
Cell Processor
Abstract
Real-time computing is the study of hardware and software systems that are subject to a “real-time constraint” - i.e., strict deadline guarantees. With uncontrollable cache and front side bus, in the modern computer architectures, the estimation
of a tight bound, worst case execution time (WCET) is difficult. The new generation computer architecture, Cell Broadband Engine Architecture (CBEA), has a software controlled front side bus (i.e. Element Interconnect Bus) that helps
moderate the unpredictable task execution time problem. The CBEA is a heterogeneous chip system containing one Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs), each having an internal independent local storage memory.
In this thesis, using CBEA as a platform, I implemented an interrupt based scheduling framework that uses Element Interconnect Bus (EIB) in a temporally predictable manner. The framework is built by abstracting away low-level architectural
features. Experiments were also performed to show that the real-time transactions of feasible transaction sets are executed before deadline when scheduled
according to a real-time scheduling algorithm, while the same transactions can miss their deadlines when scheduled according to an arbitrary (non-real-time)
scheduling policy.
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