Soft N-modular redundancy: exploiting statistics for robust computation

Kim, Eric P.

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https://hdl.handle.net/2142/14721 Copy

Description

Title

Soft N-modular redundancy: exploiting statistics for robust computation

Author(s)

Kim, Eric P.

Issue Date

2010-01-06T16:41:53Z

Director of Research (if dissertation) or Advisor (if thesis)

Shanbhag, Naresh R.

Doctoral Committee Chair(s)

Shanbhag, Naresh R.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• fault tolerance
• low power
• algorithmic technique
• signal processing
• N-modular redundancy

Abstract

Achieving energy-efficiency in nanoscale CMOS process technologies is made challenging due to the presence of process, temperature and voltage variations. In this thesis, we present soft N-modular redundancy (soft NMR) that exploits statistics of errors due to these nanoscale artifacts in order to design robust and energy-efficient systems. In contrast to conventional NMR, soft NMR employs estimation and detection techniques in the voter. Analysis of soft NMR, NMR and ANT is given to facilitate future design of systems employing such robust techniques. We also compare NMR and soft NMR in the design of an energy-e cient and robust discrete cosine transform (DCT) image coder. Simulations in a commercial 45 nm, 1:2 V, CMOS process show that soft triple-MR (TMR) provides 10 improvement in robustness and 13% power savings over TMR at the same peak signal-to-noise ratio (PSNR) of 20 dB. In addition, soft dual-MR (DMR) provides a 2x improvement in robustness and a 35% power savings over TMR at the same PSNR of 20 dB. An FPGA implementation of the 2-D DCT showed that hardware emulation results match the RTL simulations.

Graduation Semester

2009-12

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http://hdl.handle.net/2142/14721

Copyright and License Information

Copyright 2009 Eric P. Kim

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