CACHE RECONFIGURATION WITH ADAPTIVE MAPPING FUNCTIONS

Lee, Julie

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https://hdl.handle.net/2142/124838 Copy

Description

Title

CACHE RECONFIGURATION WITH ADAPTIVE MAPPING FUNCTIONS

Author(s)

Lee, Julie

Issue Date

2023-05-01

Keyword(s)

Computer architecture; caches; reconfigurable hardware

Abstract

In modern computation, processor latency is heavily bottlenecked by memory access time. Caches provide a solution to this problem by storing frequently accessed data close to the processor. Generally, cache designs are fixed function and fixed configuration, as they are hardware-managed. However, general purpose processors are designed to service many different types of programs, which exhibit various memory access patterns that can dramatically affect their performance. Thus, a one-size-fits-all approach for caches is unsuitable. Instead, we introduce a mapping function that provides reconfiguration benefits while exploiting the underlying structure of existing cache architectures. Traditionally, caches are indexed from the same subset of bits of an address for all memory requests. Yet many applications display non-uniform distribution of accesses among cache sets. This implies that between applications, different indexing methods should be used to enhance caching benefits. With the addition of a mapping function, we are free to adapt our indexing scheme so that caches can better complement various application behaviors. In this project, we analyze different mapping functions across SPEC2006 benchmarks on the MARSSx86 CPU simulator. We identified several ideal mapping functions for SPEC workloads. The mapping function provides a base for a wide range of future extensions, including dynamic reconfiguration, ML-guided parameter identification, and heterogeneous partitioning.

Type of Resource

text

Language

eng

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