DESIGN OF A MULTI-PHASE CLOCK GENERATOR FOR HIGH-PERFORMANCE WIRELESS TRANSCEIVERS

Liu, Shuozhen

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https://hdl.handle.net/2142/124835 Copy

Description

Title

DESIGN OF A MULTI-PHASE CLOCK GENERATOR FOR HIGH-PERFORMANCE WIRELESS TRANSCEIVERS

Author(s)

Liu, Shuozhen

Issue Date

2023-05-01

Keyword(s)

CMOS Integrated Circuits, Non-Overlapping Clock Generators, Radio Frequency Integrated Circuits

Abstract

Advanced wireless transceivers implemented with Complementary Metal Oxide Semiconductors (CMOS) processes play a critical role in the next generation wireless applications, such as fifth and sixth generation (5G and 6G) wireless networks. One of the key building blocks is the non-overlapping clock generator, which creates square-wave pulses at radio frequencies at different non-overlapping phases. Specifically, non-overlapping clock generators are used in components such as mixer-first receivers, N-path filters, linear periodically time variant (LPTV) LC-delay lines, etc. The purpose of this project is to research and review state-of-the-art nonoverlapping clock generator designs, and design an eight-phase non-overlapping clock generator operating at GHz frequency in a 45nm GPDK CMOS process. Finally, the limitations of the design are studied, in terms of maximum operation frequency, rise and fall time, and power consumption.

Type of Resource

text

Language

eng

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