Design and Implementation of Equalizer and its Automatic Porting
Lu, Chengjun
Loading…
Permalink
https://hdl.handle.net/2142/124817
Description
Title
Design and Implementation of Equalizer and its Automatic Porting
Author(s)
Lu, Chengjun
Issue Date
2023-05-01
Keyword(s)
signal integrity problems, CTLE circuit with a differential amplifier topology
Abstract
High-speed serial links are crucial to wired communication and modern electronic devices. As a result, there is an increasing demand for high-bandwidth wireline communication systems. However, non-idealities, including channel losses, jitter, and intersymbol interference (ISI), will influence the signal quality and raise signal integrity problems. This thesis will study their effects and propose a solution to make design improvements. It will design a power-efficient CTLE circuit with a differential amplifier topology to combat channel loss and transfer it to other technology nodes automatically.
Use this login method if you
don't
have an
@illinois.edu
email address.
(Oops, I do have one)
IDEALS migrated to a new platform on June 23, 2022. If you created
your account prior to this date, you will have to reset your password
using the forgot-password link below.
