An on-chip equivalent-time measurement system for high-speed signals
Ng, Andrew C.
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Permalink
https://hdl.handle.net/2142/124599
Description
Title
An on-chip equivalent-time measurement system for high-speed signals
Author(s)
Ng, Andrew C.
Issue Date
2024-05-01
Director of Research (if dissertation) or Advisor (if thesis)
Hanumolu, Pavan K
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
On-chip measurement
Abstract
This thesis explores the design and implementation of an on-chip measurement system tailored for high-speed integrated circuits and systems. The focus of this research lies in overcoming the limitations posed by traditional off-chip measurement techniques by eliminating analog signal chains between a signal's genesis and the measurement equipment, and providing increased observability for on-chip signals. The proposed system employs an equivalent-time measurement methodology to address these challenges, providing an approach to accurately capture and digitize high-speed signals directly at the source.
The significance of in situ measurement is underscored, particularly in the context of die-to-die communication signals, where accurate characterization requires faithful measurement of on-chip signals. By their nature, traditional measurement methodologies fail to achieve this, leading to inaccuracies in signal representation and, consequently, hindering the development and optimization of high-speed integrated circuits.
The devised on-chip measurement system is composed of three key blocks: a programmable delay, a programmable voltage source, and a comparator. Leveraging these three components, the system facilitates measurements by sampling signals at programmable time and voltage coordinates from within the integrated circuit itself. This approach aims to mitigate the distortions introduced by off-chip measurements, providing a more faithful representation of the signal behavior in its native on-chip environment.
The system's constituent parts have been verified and characterized at the transistor level and imperfections have been incorporated into corresponding behavioral models. The full system functionality has been verified at the behavioral level and post-processing of collected data enable average waveform and statistical eye diagram construction. The system has been designed using Intel's 22nm fin-FET technology.
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