Towards real-time high-resolution edge detection: A highly efficient FPGA implementation of the Canny algorithm
Zhang, Zhengyang
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Permalink
https://hdl.handle.net/2142/124588
Description
Title
Towards real-time high-resolution edge detection: A highly efficient FPGA implementation of the Canny algorithm
Author(s)
Zhang, Zhengyang
Issue Date
2024-04-30
Director of Research (if dissertation) or Advisor (if thesis)
Kindratenko, Volodymyr
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
FPGA implementation
Canny edge detection algorithm
High-level synthesis (HLS)
Abstract
With the rapid development of computer vision technology in recent years, image edge detection has been playing an increasingly important role in fields such as object recognition, image segmentation, and image enhancement. The Canny edge detection algorithm stands out among various edge detection algorithms for its accuracy and robustness. However, its high computational complexity makes it challenging to meet the requirements of real-time processing. This work presents an optimized FPGA-based design for Canny edge detection that significantly enhances execution efficiency by leveraging High-level Synthesis (HLS) to achieve pipelined computation and communication.
The main contributions of this work are as follows: (1) proposing a streaming-based data movement strategy combined with a multi-sliding window architecture, significantly enhancing data throughput and computational efficiency; (3) constructing fully pipelined compute units to achieve high-throughput edge detection processing; (4) deploying our design on the OpenCL framework and testing its performance on actual hardware, further enhancing the acceleration effect through OpenCL's out-of-order execution feature. After optimization, the proposed design achieves an execution latency of 61 microseconds for edge detection on 512×512 resolution images when operating at 300MHz, with a simulation latency of 32.8 microseconds at the same frequency, representing a 3.67-fold improvement over the fastest open-source FPGA implementation and meeting the requirements for real-time processing.
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