Heterogeneous CPU-FPGA system framework and scheduler

Li, Luoyan

Permalink

https://hdl.handle.net/2142/124460 Copy

Description

Title

Heterogeneous CPU-FPGA system framework and scheduler

Author(s)

Li, Luoyan

Issue Date

2024-05-03

Director of Research (if dissertation) or Advisor (if thesis)

Kindratenko, Volodymyr

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

Heterogeneous Computing, CPU+FPGA, scheduler, OpenCL

Abstract

In this work, we explore two critical aspects of heterogeneous CPU-FPGA systems within high-performance computing: the optimization of single tasks and the effective scheduling of heavy workloads. We consider systems that consist of general-purpose units such as CPUs, and specialized accelerators, such as FPGAs, to boost computational efficiency and throughput. Our research centers on exploiting the multithreading of CPUs and the pipelined architecture of FPGAs. We specifically focus on the distribution of image processing tasks using the Canny edge detection algorithm as a representative test case to assess system performance under various workload conditions. Through a comprehensive series of experiments executed within the OpenCL framework, we assess the effectiveness of our task partitioning strategy alongside various task distribution methods between CPUs and FPGAs. These experiments are designed to explore the potential of integrating multi-thread CPUs with pipelined FPGAs to optimize the processing of multiple tasks. We also provide insights into the method of optimizing task allocation to minimize latency and maximize throughput, showcasing the potential of heterogeneous systems in handling computationally intensive applications efficiently.

Graduation Semester

2024-05

Type of Resource

Thesis

Copyright and License Information

Copyright 2024 Luoyan Li

Owning Collections