Design and analysis of a 1.28ghz charge pump phase-locked loop in 180nm technology node
Wang, Qiuyu
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https://hdl.handle.net/2142/124373
Description
Title
Design and analysis of a 1.28ghz charge pump phase-locked loop in 180nm technology node
Author(s)
Wang, Qiuyu
Issue Date
2024-04-30
Director of Research (if dissertation) or Advisor (if thesis)
Schutt-Ainé, José E
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Phase-locked loop
PLL
Mixed-signal IC design
High-speed link
Abstract
This thesis presents readers, especially undergraduate electrical engineering students in their junior or senior years who have solid background knowledge in Integrated Circuits (IC) design and strong passion in the semiconductor industry, with some flavors of the fundamentals of the mixed-signal IC design of a phase-locked loop (PLL) implemented in 180nm technology node and operated at a center frequency of 1.28GHz. It begins by introducing the applications and motivations of PLLs. The thesis then moves on by diving deep into the discussion of each of the PLL component’s intuition, schematic, characteristic, and linear model. Afterwards, a complete analysis of PLL is conducted, including its block diagram, linear model, stability, and characteristics, etc. The thesis finishes with the conclusion and discussion of future work to improve the PLL design.
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