An interleaved multilevel inverter topology for high-frequency low-inductance motors

Bali, Arjit

Permalink

https://hdl.handle.net/2142/122005 Copy

Description

Title

An interleaved multilevel inverter topology for high-frequency low-inductance motors

Author(s)

Bali, Arjit

Issue Date

2023-12-07

Director of Research (if dissertation) or Advisor (if thesis)

Stillwell, Andrew R

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• Multilevel inverter
• flying capacitor multilevel converter
• hybrid active neutral point clamped converter
• interleaved hybrid active neutral point clamped converter
• dc-link capacitor
• interleaving
• voltage source inverter

Abstract

Electric vehicle and electric aviation applications require lightweight electro-mechanical energy conversion; however, passive components in the drive system can constrain the power density. Slotless machine construction can attain high power density, but such designs result in very low per-phase machine inductances. The reduced inductance imposes additional filtering requirements between the inverter and motor, which lower the power density benefits gained from the slotless design used. Furthermore, the dc-link capacitor within the inverter increases significantly the overall weight and volume. In this work, the advantages of interleaving multilevel topologies are discussed, and an interleaved hybrid active neutral point clamped (I-HANPC) converter is proposed to achieve reduced output filter sizes and enable a smaller dc-link capacitor. The design is demonstrated with a 7-level I-HANPC experimental hardware prototype that attains a peak efficiency of 98.8% with low output total harmonic distortion.

Graduation Semester

2023-12

Type of Resource

Thesis

Handle URL

https://hdl.handle.net/2142/122005

Copyright and License Information

Copyright 2023 Arjit Bali

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