Design techniques for high-speed wireline receivers

Wang, Tianyu

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https://hdl.handle.net/2142/117599 Copy

Description

Title

Design techniques for high-speed wireline receivers

Author(s)

Wang, Tianyu

Issue Date

2022-12-05

Director of Research (if dissertation) or Advisor (if thesis)

Hanumolu, Pavan Kumar

Doctoral Committee Chair(s)

Hanumolu, Pavan Kumar

Committee Member(s)

• Schutt-Aine, Jose
• Rosenbaum, Elyse
• Zhou, Jin

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• Electrical receiver
• display driver
• equalization
• bandwidth extension
• low-jitter CDR
• CDR sampling phase optimization
• optical receiver
• multi-stage transimpedance amplifier

Abstract

The demand of display driver IC (DDI) is expected to witness a rapid growth thanks to the growing demand for LCD panels. A DDI is the interface module between a microprocessor and the display panel pixels. With the ever-increasing demand of higher resolution, refresh rate, and color depth in the display, the DDI must accommodate the increasing demand of data rate and provide equalization to wide variety of channel losses. In contrast to the aggressively increasing demand of performance, the DDI is limited to low-cost technologies. In this thesis, a high-speed DDI is presented to support next-generation 8 K ultra-highdefinition TVs. The receiver supports error-free communication between the timing controller and the display driver ICs across various channels. Because the receiver must be co-integrated with pixel drivers in the display driver IC, it must be implemented in a process with high voltage devices, which poses significant challenges in achieving beyond 5 Gb/s operation. We propose techniques for overcoming such process-induced speed limitations. They include a level-shifting passive continuous-time equalizer (CTLE), an active CTLE with extended bandwidth using a negative capacitor, a speculative decision feedback equalizer with a down-sampled edge-sampling path, and a low-dropout regulator with parallel error amplifiers to achieve all-band power supply rejection. A reference-less clock and data recovery circuit with a new frequency detector is also described. Fabricated in a 180 nm CMOS process, the prototype receiver operates at 5.2 Gb/s and can compensate up to 29 dB channel loss while consuming 120 mA from a 1.8 V supply. The prototype DDI provided competitive performance as well as feedback to the existing bottlenecks: 1) the necessity between an edge decision feedback equalizer (XDFE) and its associated power consumption and hardware complexity; 2) The DFE is incapable of removing the precursor, which has become the limiting factor of achievable eye margin. We propose to replace the XDFE with an all-digital algorithm that suppress the ISI’s impact on timing recovery by optimally estimate the timing error and suppressing the precursor by optimizing the CDR’s sampling phase with a hardware efficient on-chip eye margin monitor. With the proposed techniques, we could improve the recovered clock jitter by 28% and worst-case eye margin by more than 50%.

Graduation Semester

2022-12

Type of Resource

Thesis

Copyright and License Information

Copyright 2022 Tianyu Wang

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