Signal processing methods to enhance the accuracy of MRAM-based in-memory architectures

Ou, Han-Mo

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https://hdl.handle.net/2142/116126 Copy

Description

Title

Signal processing methods to enhance the accuracy of MRAM-based in-memory architectures

Author(s)

Ou, Han-Mo

Issue Date

2022-07-21

Director of Research (if dissertation) or Advisor (if thesis)

Shanbhag, Naresh R

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• In-memory architectures
• MRAM
• Statistical compensation
• Digital signal processing

Abstract

In-memory computing for machine learning applications has drawn much interest from researchers since its inception in 2014. In-memory computing reduces delay and energy costs, the use of non-volatile memory increases storage density, and allows the processing of large data. One major challenge of in-memory architectures is to maintain high accuracy, since they employ analog computations and therefore suffer from noise and process variations as compared to their digital counterparts. Using in-memory computing for applications requiring high accuracy, such as digital signal processing, is therefore a major challenge. In this thesis, we discuss the impact of parasitic resistances in resistive memory-based in-memory architectures for matrix-vector multiplications. Parasitic wire resistances between memory cells, although small in value, have significant effects on the accuracy. This problem limits the ability to scale up the popular in-memory current-summing architectures. We employ a signal processing based-approach to the problem. A signal model of the in-memory bank is constructed from circuit analysis of the memory array and is subsequently used to employed to develop compensation methods. Our proposed activation scaling compensation achieves an 18 dB to 21 dB gain in signal-to-distortion ratio and is shown to substantially aid in-memory computing-based digital filtering. Activation scaling's low overhead (<0.01%) makes it suitable for on-chip implementation on future resistive memory-based designs.

Graduation Semester

2022-08

Type of Resource

Thesis

Copyright and License Information

Copyright 2022 Han-Mo Ou

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