Stability analysis of voltage-in-current latency insertion method

Wang, Qingyi

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https://hdl.handle.net/2142/115759 Copy

Description

Title

Stability analysis of voltage-in-current latency insertion method

Author(s)

Wang, Qingyi

Issue Date

2022-04-29

Director of Research (if dissertation) or Advisor (if thesis)

Schutt-Ainé, José E

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• Latency insertion methods
• Circuit simulation

Abstract

As the semiconductor industry produces more transistors with higher frequencies and a more compact chip design, the demand for a novel simulation tool capable of simulating large-scale circuits both quickly and accurately has been increasing. The latency insertion method (LIM) has been proposed as a viable alternative to the conventional SPICE simulator for the simulation of large networks as it enables linear numerical complexity and achieves significant speed improvement. In this thesis, an improved version of the LIM called the voltage-in-current latency insertion method (VinC LIM) is discussed. Special attention is devoted to the stability analysis of VinC LIM. We prove and demonstrate that VinC LIM overcomes the time step size limitation that the basic LIM faces and improves the stability significantly. With the larger time steps, VinC LIM can allow the simulation to finish in a much shorter time without suffering from the stability limitation.

Graduation Semester

2022-05

Type of Resource

Thesis

Copyright and License Information

Copyright 2022 Qingyi Wang

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