University of Illinois Urbana-Champaign

A Translation Validation Algorithm for LLVM Register Allocators

Lin, Zhengyao; Kasampalis, Theodoros; Adve, Vikram

Content Files
lin-kasampalis-adve-2021-tr.pdf

Permalink

https://hdl.handle.net/2142/112734

Description

Title
A Translation Validation Algorithm for LLVM Register Allocators
Author(s)
  • Lin, Zhengyao
  • Kasampalis, Theodoros
  • Adve, Vikram
Issue Date
2021
Keyword(s)
  • Translation validation
  • Register allocation
  • LLVM
Date of Ingest
2021-11-12T03:09:27Z
Abstract
Register allocation is a crucial and complex phase of any modern production compiler. In this work, we present a translation validation algorithm that verifies each single instance of register allocation. Our algorithm is external to the compiler and independent of the register allocation algorithm. We support all major register allocation optimizations such as live range splitting, register coalescing, and rematerialization. We developed a prototype of this approach for the production-quality register allocation phase of LLVM. We evaluated this prototype for compiling the source code of SPECint 2006 benchmark, and we were able to verify the register allocation of over 88% of supported functions in the benchmark, using all 4 register allocators available in LLVM 5.0.2.
Type of Resource
text
Genre of Resource
technical report
Language
en
Permalink
http://hdl.handle.net/2142/112734

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Research and Tech Reports - Computer Science PRIMARY