Investigation of system-level ESD-induced failures

Vora, Sandeep Gautam

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https://hdl.handle.net/2142/109333 Copy

Description

Title

Investigation of system-level ESD-induced failures

Author(s)

Vora, Sandeep Gautam

Issue Date

2020-09-04

Director of Research (if dissertation) or Advisor (if thesis)

Rosenbaum, Elyse

Doctoral Committee Chair(s)

Rosenbaum, Elyse

Committee Member(s)

• Hanumolu, Pavan
• Zhou, Jin
• Schutt-Ainé, José

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• Electrostatic Discharge
• ESD
• IC
• Reliability
• EM simulation

Abstract

Electrostatic discharge (ESD) is a phenomenon that can adversely impact the operation of systems. ESD is a short duration, high current stress which can cause the permanent failure of a system or temporary glitches in a system. Soft failures include any recoverable system malfunction, from resets to loss of stored data. They can be caused by noise entering signal pins or by supply voltage fluctuations. Soft failures have previously been studied by using test structures to identify failure mechanisms or actual products to identify the types of soft failures that occur. These models are either simplified or offer little to no insight into the cause of the soft failures. The first part of this dissertation addresses soft failures within a fully functional semi-custom microcontroller. This allows for both an understanding into the exact causes of soft failures as well as testing for effects of soft failures from ESD on operating software. The second part of this work focuses on latch-up in reverse body biased core circuitry. Latch-up is a phenomenon where parasitic devices within a CMOS structure turn on and stay on, shunting current from power to ground, often causing permanent failure. Latch-up has often been looked at from a substrate current injection point of view, however, measurement of a reverse body biased chip shows that latch-up can occur due to supply bounce. An analytic model and SPICE simulation verify the phenomenon, and with the help of simulation, methods of increasing robustness are discussed.

Graduation Semester

2020-12

Type of Resource

Thesis

Permalink

http://hdl.handle.net/2142/109333

Copyright and License Information

Copyright 2020 Sandeep Vora

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