Extending secure and trusted computation to FPGA accelerators
Ren, Wei
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https://hdl.handle.net/2142/109322
Description
Title
Extending secure and trusted computation to FPGA accelerators
Author(s)
Ren, Wei
Issue Date
2020-08-17
Director of Research (if dissertation) or Advisor (if thesis)
Chen, Deming
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Security
Trusted Computation
FPGA
Abstract
As the demand for computation power grows rapidly, the need for security and privacy has become stronger in cloud computing and heterogeneous systems. Several cloud and data centers have already started deploying Field Programmable Gate Arrays (FPGAs) as reconfigurable accelerators with high performance and energy efficiency. However, the current infrastructure design provides little or no support for security in external accelerators. Existing trusted computing solutions such as Intel SGX or ARM TrustZone target at CPU-only environments, making external accelerators and peripheral devices unprotected. This work proposes a new scheme to extend trust computing for FPGA accelerators. The scheme consists of a security manager (SM) with hardware root of trust through standard cryptographic primitives and remote attestation of the SM as well as the custom accelerators. Our prototype implementation of the FPGA enclave framework minimized the performance overhead (due to the security features) compared to a state-of-the-art CPU-based enclave framework, Intel SGX, while enjoying the benefit of improved performance through hardware acceleration. From our evaluation results, an accelerated histogram application running in our FPGA enclave environment achieved a 6.2x performance speedup on average compared to the same application running inside an Intel SGX enclave.
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