A study of worst-case integrated circuit optimization using iEDISON3.0

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https://hdl.handle.net/2142/108870

Title: A study of worst-case integrated circuit optimization using iEDISON3.0
Author(s): Bieker, John Joseph
Issue Date: 1994
Director of Research (if dissertation) or Advisor (if thesis): Kang, Sung-Mo
Discipline: Electrical Engineering
Degree Granting Institution: University of Illinois at Urbana-Champaign
Degree Name: M.S. (master's)
Degree Level: Thesis
Keyword(s): Circuit optimization
Language: en
Type of Resource: text
Permalink: http://hdl.handle.net/2142/108870

Graduate Theses and Dissertations at Illinois