Boosting static timing analysis with programming and algorithmic approaches
Guo, Guannan
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https://hdl.handle.net/2142/108153
Description
Title
Boosting static timing analysis with programming and algorithmic approaches
Author(s)
Guo, Guannan
Issue Date
2020-05-11
Director of Research (if dissertation) or Advisor (if thesis)
Wong, Martin D.F.
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Static Timing Analysis
Parallel Programming
Abstract
The increasing complexity in digital design has spurred demand for faster design closure. As a primary timing measurement tool frequently used in design stage and optimization stage, static timing analysis has become one of the major performance bottlenecks in digital design. We study a novel parallel programming model and algorithm to boost timing analysis. As multi-core systems have become common in modern electronics, how to fit timing analysis into the multithreading environment is a trending research topic. We explore this direction with a new task-based multithreading framework and demonstrate its superior efficiency over existing tools. Critical path generation is a major objective timing analysis. Optimization tools always need to report on critical paths under several path constraints. We propose a general path search algorithm which can fulfill all practical path constraints and outperforms an industrial timing analysis tool. Combining the tasks proposed above, we aim to improve the efficiency of static timing analysis with both a new programming framework and new algorithm.
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