High-performance reference frequency generation techniques

Megawer, Karim M.

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https://hdl.handle.net/2142/108103 Copy

Description

Title

High-performance reference frequency generation techniques

Author(s)

Megawer, Karim M.

Issue Date

2020-04-13

Director of Research (if dissertation) or Advisor (if thesis)

Hanumolu, Pavan K

Doctoral Committee Chair(s)

Hanumolu, Pavan K

Committee Member(s)

• Shanbhag, Naresh R
• Schutt-Aine, Jose E
• Zhou, Jin

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• Crystal oscillator (XO)
• digitally controlled oscillator (DCO)
• duty-cycle correction
• frequency quadrupler
• injection-locked clock multiplier (ILCM)
• jitter
• least mean square (LMS)
• ring oscillator (RO)
• startup time

Abstract

Low-noise high-frequency fast-startup reference frequency generators are needed in high-performance power-efficient communication systems. Frequency synthesizers that generate high-frequency clocks in modern wireline/wireless transceivers require high-frequency reference clocks to achieve excellent noise performance. In the first part of this work, we present ways to generate such reference clocks at 4 times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216MHz reference clock with an integrated jitter of 77fsrms is generated from a 54MHz Pierce XO. A ring oscillator based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65nm CMOS process, the proposed clock multiplier occupies an active area of 0.16mm2 and achieves 366fsrms integrated jitter at 4.752GHz output frequency while consuming 6.5mW power from a 1.0V supply of which 1.5mW is consumed in the quadrupler. Heavily duty-cycled communication systems that implement aggressive dynamic power management schemes to reduce average power consumption require fast-startup reference clocks which demand fast-startup crystal oscillators. In the second part of this thesis, we present ways to improve the startup time of crystal oscillators. Using a two-step injection technique in a three-step process, the proposed technique reduces the crystal oscillator startup time to within 1.5x the theoretical minimum. By solving the differential equation governing a crystal resonator under injection for arbitrary injection frequency, the behavior of energy buildup inside a crystal resonator is analyzed and used to determine optimum injection time as a function of the desired crystal oscillator steady-state amplitude and injection frequency error. Bounds on tolerable injection frequency error to guarantee the existence of optimal timing are provided. Fabricated in a 65nm CMOS process, the proposed 54MHz fast-startup crystal oscillator occupies an active area of 0.075mm2 and achieves a startup time of less than 20us across a temperature range of -40oC to 85oC while consuming a startup energy of 34.9nJ and operating from a 1.0V supply.

Graduation Semester

2020-05

Type of Resource

Thesis

Permalink

http://hdl.handle.net/2142/108103

Copyright and License Information

Copyright 2020 Karim M. Megawer

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