Development and analysis of a parallelized direct position estimation-based GPS receiver implementation

Peretic, Matthew

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https://hdl.handle.net/2142/105723 Copy

Description

Title

Development and analysis of a parallelized direct position estimation-based GPS receiver implementation

Author(s)

Peretic, Matthew

Issue Date

2019-07-18

Director of Research (if dissertation) or Advisor (if thesis)

Gao, Grace Xingxin

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• Global Positioning System (GPS)
• Global Navigation Satellite System (GNSS)
• Direct Position Estimation (DPE)
• GPS Receiver
• Parallel Programming

Abstract

Theoretical results conclude that one-step Direct Position Estimation (DPE)-based Global Navigation Satellite System (GNSS) receivers can achieve more accurate localization than their two-step counterparts. However, numerical solutions to DPE equations and approximations made for those equations introduce new effects that can reduce the accuracy improvement that such a one-step receiver may provide. This work examines effects that arise from those numerical solutions to DPE equations and from the approximations made for those equations. In light of the theoretical formulation of the DPE algorithm, resultant insights for design decisions of a DPE receiver implementation are presented, stemming from analysis of the localization and processing time results of a parallelized DPE receiver implementation developed specifically for this work. Additionally, a modular software architecture for the custom DPE receiver implementation and parallelization of portions of the DPE receiver algorithm for GPU operation are also proposed.

Graduation Semester

2019-08

Type of Resource

text

Permalink

http://hdl.handle.net/2142/105723

Copyright and License Information

Copyright 2019 Matthew Peretic

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