Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology
Rajwardan, Ashwarya
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https://hdl.handle.net/2142/104803
Description
Title
Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology
Author(s)
Rajwardan, Ashwarya
Issue Date
2019-04-11
Director of Research (if dissertation) or Advisor (if thesis)
Schutt-Ainé, José E.
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
DFE, CTLE, Equalizer, Signal Integrity, High-speed serial link
Abstract
This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz.
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