Design of a 51.84-Mb/s Very High Speed Digital Subscriber Loop Reconfigurable Receiver Core

Tschanz, James Willard

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https://hdl.handle.net/2142/103950 Copy

Description

Title

Design of a 51.84-Mb/s Very High Speed Digital Subscriber Loop Reconfigurable Receiver Core

Author(s)

Tschanz, James Willard

Issue Date

1999-09

Keyword(s)

• Digital subscriber loop
• Adaptive equalizers
• FIR digital filters
• Dynamic reconfiguration
• CMOS digital integrated circuits
• ASIC design methodology

Publisher

Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Series/Report Name or Number

Coordinated Science Laboratory Report no. UILU-ENG-99-2227, DAC-76

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/103950

Sponsor(s)/Grant Number(s)

National Science Foundation / MIP 96-23737

Owning Collections