Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Hamzaoglu, Ilker
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https://hdl.handle.net/2142/103949
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Title Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits Author(s) Hamzaoglu, Ilker Issue Date 1999-10 Keyword(s) Automatic test generation Test application time reduction Test set compaction Design for testability Built-in self test Combinational circuits Sequential circuits Publisher Coordinated Science Laboratory, University of Illinois at Urbana-Champaign Series/Report Name or Number Coordinated Science Laboratory Report no. UILU-ENG-99-2228, CRHC-99-15 Type of Resource text Language en Permalink http://hdl.handle.net/2142/103949 Sponsor(s)/Grant Number(s) Semiconductor Research Corp. / SRC 97-DS-482 PATEL DARPA / DABT63-95-C-0069
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